We have bought an AD-FMCOMMS3-EBZ together with a ZedBoard. It was nice to have all the system on the SD-card, and to start using Gnuradio.
I have downloaded the reference design, and after some time I could compile the FPGA code (make fmcomms2.zed) with Vivado 2016.2. It took about 15 minutes! I have an i5-4460 CPU @ 3.2 GHz and 8 GB RAM. After that I was able to make a tiny modification of the "system_top.v" (to drive a LED from a switch). It took again 15 minutes to compile! Later I tried to modify other source files in the project, but I was somehow lost in the folder hierarchy, and surprised by the fact that some source files are copied by the Makefile. Then I copied the relevant source files of the project to a Windows machine, and after a few tries I could compile it with Vivado 2017.2. It still take about 15 minutes (the PC is comparable to the Linux one). Now I am able to change code more deeply, but I wonder why the compilation time is so long. I have tested the incremental compilation, it does not help so much. I read somewhere that Vivado does not use efficiently the multicore CPU, but I did not try to limit to one core. Strangely it uses all four cores at about 25 % for some time during the compilation.
Synthesis takes about 9 minutes, and implementation about 6.
How to speed up? How to tell the synthesis engine that most of the design did not change?