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What is the minimum sample frequency that can be used to display the samples in the graph of Visual Analog or that the HSC-ADC_EVALCZ evaluation kit can process?

Question asked by oceley on Oct 10, 2017
Latest reply on Oct 18, 2017 by DougI

I am currently using the AD9637-80EBZ evaluation kit together with the HSC-ADC-EVALCZ evaluation kit and Visual Analog software. When I clock the AD9637-80 at 80MHz and use the Octal_High_Speed.bin binary file to program the FPGA the graph inside Visual Analog updates correctly. (just a plain visualization of the input sine wave of the AD9637-80EBZ evaluation kit) But when I lower the clock of the ADC to 20MHz either by supplying a 20MHz clock with the SMA connector (jumper was removed) or by using the AD9637's internal clock divider. the Visual Analog software stops updating the graph.

I read in in the quickstartguide_ad9257_ad9637_prb.pdf on the AD9637-80EBZ wiki page that "if sampling at less than 30Msps Octal_Low_Speed.bin should be loaded in the FPGA". I loaded the Octal_Low_Speed.bin binary file into the FPGA but the graph still does not update the graph whilst the datasheet of the AD9637 states that the minimum sample frequency is 10Msps. So my question is: What is the minimum sample frequency that can be used to display the samples in the graph of Visual Analog or that the HSC-ADC_EVALCZ evaluation kit can process?

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