We have found a problem with a PLO which is designed using a solution based on a HMC704LP4E PLL and a HMC531LP5E VCO. The signal reference for locking the PLL is a 100MHz signal from a VCXO which is locked to a 10 MHz external signal through an ADF4002BRUZ PLL.
Initially we have designed a PLO (it will be called PLO_V1), which has been manufactured around 100 units. These PLOs have been working without problem.
After that, it has been designed a new version of the PLO (it will be called PLO_V2) which includes an internal 10 MHz OCXO. The schematic and the PCB design it almost identical between PLO_V1 and PLO_V2, without considering the additional components used in PLO_V2 to include the OCXO. The main difference is that 100 MHz VCXO in PLO_V1 is soldered over the top of the PCB and in PLO_V2 is soldered at bottom of the PCB.
The problem we found with version PLO_V2 is that there is a degradation in the phase noise behaviour, but this degradation is only observed when using as fractional, if the PLL is used as integer the phase noise is the same for both versions.
We have assembled two units of PLO_V2, one with internal 10 MHz OCXO and the other without mounting all the components for the OCXO and using an external 10 MHz reference to lock. In this second assembly, we have the same components as in PLO_V1. The wrong behaviour is the same for both configurations, it is not noticed any difference.
In figure1 and figure2, it can be observed the phase noise of PLO_V1 for a frequency of 14 GHz (integer) and for a frequency of 14.025 GHz (fractional). The registers used in each case are the following:
F=14 GHz à 00000000,01000001,02000001,03000023,04000000,05000005,060307CA,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000008,0F000081
F=14.025 GHz à 00000000,01000002,02000001,03000023,04100000,05006095,06030F4A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081
These should be the phase noise results we could expect for PLO_V2 using the same registers. However, as it can be observed in figure3 and figure4, for the frequency of 14 GHz the phase noise is the same and for a frequency of 14.025GHz the phase noise is rather worse. The registers are the same that in PLO_V1
We have been doing several tests to find which could be the reason to this problem, and we have found a strange situation in PLO_V2. If we sent the registers 00000000,01000001,02000001,03000023,04100000,05006095,0603074A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081, the PLO is not locked as it is logical because it has been disable the modulator through signal frac_rstb (bit 11 register 06). After that is sent again the 14.025 GHz registers (00000000,01000002,02000001,03000023,04100000,05006095,06030F4A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081) the PLO takes about 5 seconds to lock and the phase noise is OK as it can be observed in figure5. Now, if is send again the same registers after about other 5 seconds the phase noise is degraded again as in figure6.
We can understand this behaviour because the registers programmed in the PLL are exactly the same.
We have been doing tests with other register values and we have found one register combination where the PLO is locked to 14.025 GHz and the phase noise is OK as in figure7. The registers used in this case are:
With these registers we have two problems, there are some spurious at 6.27MHz very high (figure8) which are not admissible in our application and we have seen that in this configuration we are using the Delta Sigma Modulator Type in a configuration ‘reserved’ as it is indicated in datasheet (bits [3:2] of register 06)
We would appreciate if you could give us any advice, about which could be the problem we have or any recommendation for locking the PLL to a frequency of 14.025 GHz. If you need any additional information please let us know it. Thanks