I am in the process of porting the ADI's AD9739A-FMC reference design for ZC706 to ZC702. I have Vivado 2016.2 on my Windows 7 (x64) machine and compiling on hdl_2016_r2 branch using Cygwin(x64). I have successfully followed Istvan's instructions (given here) on how to change the IO constraints and system top file. The project compilation results with an error that points out that timing constraints are not met.
The only changes I have made are re-mapping IO constraints and removing extra hdmi_data bits from system_top. I am beginning to think that I might be missing a clock related problem, but unsure how I should deal with it. I have attached Vivado and timing logs.
I have found a couple of timing constraint related problems on forums but none of the solutions seemed to apply to my case, since the supposed patch for those problems are already applied to hdl_2016_r2 branch. I will try to compile ZC706 reference design with an evaluation license to see if same problem occurs.