phintena

Bug: Interrupt Handling, CrossCore, ADSP-21469

Discussion created by phintena on Oct 9, 2017
Latest reply on Oct 22, 2017 by phintena

Good Morning,

the documented way for handling interrupts in an CrossCore project is using adi_int.h and adi_int_InstallHandler. For serving an interrupt the CPU pushes STS and branches from the interrupt vector associated with the interrupt to  __dispatcher_XXX, where XXX is the name of the interrupt. The dispatcher pushes the registers PX1, PX2, R4 (all 40 bits), R8 (all 40 bits) and R12 (all 40 bits) onto the C runtime stack. Than it branches to the procedure registered with adi_int_InstallHandler. In order not to clobber a DAG2 Index register, this branch is coded as first a push of the procedure's address onto the PC stack and then an RTI instruction.

Saving only these few registers is sufficient for an application where all activities are performed by the interrupt service routines only and the main program consists of an empty infinite loop only. Furthermore nested interrupts are not possible.

For more general systems interrupt service routines must save and restore the contents of all registers they use. CrossCore's C compiler supports this with #pragma interrupt_complete_nesting and #pragma interrupt_complete. The documentation for these however is rather short and sort of discourages their use.

In my opinion the use of adi_int.h ins encouraged without stating the rather severe limitations put on the systems which use it. The more general mechanism using the pragmas is not realy described at all.

What I like to see is an in-depth discussion (including sketches of the machine code) of all possibilities for handling interrupts in CrossCore.

What do you think?

 

Peter

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