how much time/clock cycles will AD9850 take to update frequency on a 125MHz source?
A frequency change has a minimum output latency of 18 clock cycles.
Thanks Mark. I have some more doubts
1. Is this 18 clock latency is present in serial mode also? In data sheet output latency is written in parallel mode's table.
2. I have calculated total time taken for writing and updating the frequency in parallel mode as 5clks(40 bit) + 1clock(FQ-UD) + 18clks latency = 24clocks. Is this correct?
3. In serial mode 40 clks(40 bits) + 1clk(FQ_ud) = 41clks. Is serial mode has latency?
4. if i change the frequency and phase will it take 18clks + 13 clks ?
1. This latency is for parallel mode.
2. Yes. This would be the minimum.
3. None. Since there is no latency indicated on the data sheet.
4. I think the range for the change in frequency and phase, would be 18clks as minimum and 18clks + 13clks as maximum.
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