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Help:AD9984A in 1080i60

Question asked by Chilton on Nov 2, 2011
Latest reply on Nov 3, 2011 by Chilton

When i use 1080i60/50(YUV) as input signal,the output image continuous shake up an down

(the function of my board is YUV to HDMI, AD9984 is used as YUV receiver and the HDMI transmitter is Sil9134 )

 

The same situation does not appear in the combination of the TVP7002 and Sil9134.

 

The picture below is the waveform of HSYNC and VSYNC.

 

Register configuration:

    ad9984_wr(0x01,0x89);
    ad9984_wr(0x02,0x80);
    ad9984_wr(0x03,0xA8);
    ad9984_wr(0x04,0x80);//Phase Adjust

    ad9984_wr(0x05,0x40);//gain and offset
    ad9984_wr(0x06,0x00);
    ad9984_wr(0x07,0x40);
    ad9984_wr(0x08,0x00);
    ad9984_wr(0x09,0x40);
    ad9984_wr(0x0A,0x00);

    ad9984_wr(0x0B,0x40);
    ad9984_wr(0x0C,0x00);
    ad9984_wr(0x0D,0x00);
    ad9984_wr(0x0E,0x80);
    ad9984_wr(0x0F,0x40);
    ad9984_wr(0x10,0x00);

    ad9984_wr(0x11,0x20); //Sync Separator Threshold    
    ad9984_wr(0x12,0xC8);
    ad9984_wr(0x13,0x2C);//Hsync Duration  20
    ad9984_wr(0x14,0xCC);
    ad9984_wr(0x15,0x06);//Vsync Duration
    ad9984_wr(0x16,0x04);//Precoast
    ad9984_wr(0x17,0x04);//Postcoast
    ad9984_wr(0x18,0x0A);//Coast and Clamp select
    ad9984_wr(0x19,0x28);//this reg also affects the luma

    ad9984_wr(0x1A,0x20);
    ad9984_wr(0x1B,0xF3);//Clamp and Offset
    ad9984_wr(0x1C,0xFF);
    ad9984_wr(0x1D,0x78);//128mV trigger
    ad9984_wr(0x1E,0xE4);//SOG select and filter
    ad9984_wr(0x1F,0xB3);//4:2:2 YCbCr mode  
    ad9984_wr(0x20,0x03);//clock select 
    ad9984_wr(0x21,0x20);
    ad9984_wr(0x22,0x32);
    ad9984_wr(0x23,0x14);//Sync Filter Window Width
    ad9984_wr(0x28,0xBF);
    ad9984_wr(0x29,0x02);

    ad9984_wr(0x2C,0x00);// Auto-Offset 
    ad9984_wr(0x2D,0xE8);
    ad9984_wr(0x2E,0xE0);
    ad9984_wr(0x34,0x00);//SOG Filter Disable
    ad9984_wr(0x36,0x00);//Disable low VCO gear
    ad9984_wr(0x3C,0x0E);//Auto Gain
    ad9984_wr(0x3C,0x00);

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