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AD9361 BBPLL Wrong Frequency

Question asked by Matty on Oct 6, 2017
Latest reply on Oct 19, 2017 by Vinod

I am debugging a PCB with several AD9361 chips. Most of these PCBs worked, but one is giving trouble. On this PCB, the clk_out frequency on only one AD9361 chip is correct at 30.72 MHz, and it is about 29 MHz on several of the other chips. The BPPLL Lock bit (D7) in register 5E is always on indicating the BBPLL is in lock. When I change the desired frequency slightly via the ad9361_set_rx_sampling_freq (ad9361_phy,   31000000) command then the clk_out on the bad chips goes to exactly half the desired frequency.  Based on these symptoms, could you shed any light on what may be wrong with the PCB ?

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