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[ADV7180] Relationship between "Vertical Lock Range" spec and IN_LOCK register.

Question asked by Tamu on Oct 6, 2017
Latest reply on Oct 19, 2017 by Tamu

Hello,

 

I have two questions about a relationship between "Vertical Lock Range" spec and IN_LOCK register of ADV7180.

The datasheet says "Vertical Lock Range = 40 - 70 Hz" on the "VIDEO SPECIFICATIONS" section.
My customer evaluated the spec and IN_LOCK bit.
When a CVBS signal with vertical frequency = 40Hz inputs to ADV7180 on the EVAL-BOARD, he can see the disordered image like out of lock and he can see the IN_LOCK bit indicates "LOCK (1)".

 

Questions:
Q1)  Can't "IN_LOCK" bit detect vertical out of lock?
Q2)  Is there any other status register indicates vertical lock "Vertical Lock Range 40 - 70 Hz"?
     Which register should be used when the CPU etc. wants to know whether ADV7180 is locked or not for VSYNC?

 

Thank you!
Best regards.

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