I'm currently working with a custom board design that uses a AD9361 that is being controlled by a MicroBlaze running the ADI No-OS software.
When I download the software to the FPGA using the SDK via the Xilinx JTAG programmer, everything seems to work fine. But, if I embed the same software ELF file into the bitstream by using the "Associate ELF Files..." option from the Vivado Tools menu, the software runs and displays the startup messages I have placed in the code but the AD9361 is being held in reset (resetb signal is being held low) causing the AD9361 not to get initialized.
Once I reach this state, I can load the same ELF file from the SDK GUI and the AD9361 is brought out of reset and everything works as expected.
Are there some startup / timing conditions that needs to be met or some clock-domain issues I need to be concerned about once the MicroBlaze starts running immediately after the the FPGA configuration is complete?
Is it possible that when the resetb signal is set low, the AXI-based GPIO module that controls this signal (bit14 of GPIO2) doesn't get initialized properly and when the software attempts to write to the GPIO2 Tri-State control register and/or data register the write doesn't get completed.
Any feedback would be appreciated.