AnsweredAssumed Answered

AD7734 Sync and Status

Question asked by AFrank on Oct 5, 2017
Latest reply on Oct 9, 2017 by jcolao

Does asserting the Sync signal clear the RDY status bits and the RDY line?  I am using the RDY line falling edge to interrupt my processor so I can read out the data.  After seeing the RDY go low, I take pulse the Sync line low then read the data, however, the status for each channel shows 0 in the RDY bit, how is this possible?  The data read is happening before the conversion can be completed, so why isn't the RDY bit set in the status register?


Thank you.