The AD9361 has inputs for external LO's which have minimal associated documentation. What I have been able to find is that the power level needs to be +3 dBm to -3dBm, that the signal needs to be at twice the tuned frequency, and that the maximum input frequency is 8 GHz so that this technique can only be used up to a tuned frequency of 4 GHz. I presume that the double frequency requirement is because it internally generates the I/Q LO's that go to the mixers using 2 D-flip flops in a toggle configuration, one triggering on the rising edge of the input and the other on the falling edge. The fcomms5 eval board schematic shows that it uses a dual differential clock driver IC in single-ended ended mode to generated 4 AC couple LO signals to inject into the RX and TX LO inputs of 2 different AD9361's. Therefore, I infer that the input signal does not need to be very sinusoidal. My question is, assuming that my injected signal is more like a clock than a sine wave, then does it need to have a 50% duty cycle in order to produce good quadrature I/Q LO's internally? If my description of the internal circuitry using flip-flops above is correct, then it would be important to trigger the flip-flops180 degrees out of phase to get internal LO's that are 90 degrees out of phase. Also, with AC coupled signals that are somewhere between a sine wave and a square wave that you would expect to see from a clock distribution IC at these frequencies, mismatches in the rise and fall times (or distortion of a sine wave) will alter the instants at which the DC average goes through zero on the rising and falling edges. Therefore, maintaining good quadrature performance should depend on both the duty cycle and the edge rates, or if using a true sine wave input any distortion will produce phase imbalance. Am I correct in my analysis?