I am trying to understand the relation between the input data stream which is 128bits @ 250MHz for 2 channel and the output sampling rate of 1GSPS.
Question 1: Am I right to that the FMCDAQ2 is operated in mode 5 configuration (Dual link, L.M.F. = 4.2.2.) ??
Question 2: The input 128bits corresponds to lets say 8 samples (128bit/ 16 bit =8). These 8 samples must be received at the output of DAC for both channels which are sent over four 10Gbps lanes. Mode 5 (Fig. 58 shown in data sheet of AD9144) receives the data. As I see it, we receive only 4 samples of data (64bits over 2 channels). I understood how the clocks are distributed, frame clock of 500MHz. Is the data received at edges of the Frame clock (Rising edge and falling edge) so as to output 8 samples. Am i right ?? Is there any reference. I looked into JESD204B with no reference how to achieve 1GSPS when your frame clock is 500MHz ?