I am using two double conversion receivers with PLL ADF4107. All the four PLL's (two per one receiver) have the same reference clock. While injecting RF signal (without modulation) to the receivers I expect that all the IF signal will be synchronized. I am checking the synchronization by changing the frequency of one PLL at receiver #1 and then returning back to the same PLL frequency that was before. For some reason the phase of the returned IF signal is changing each time I am changing the PLL frequency and returning back? According to the theory when using 2nd order type 2 synthesizers, the phase of the two IF signals should be synchronized.