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HMC7044 PLL2 is not locked

Question asked by fuji38 on Oct 3, 2017
Latest reply on Oct 5, 2017 by fuji38

Hello all,

 

I started using a HMC7044 evaluation board. Since there is an issue on controlling via USB-SPI, I am using a FPGA as the SPI controller. At first, as described in UG-826, I tried out the quick start configuration by extracting the register settings from the file "HMC7044_983MHz_122p88MHz_VCXO_DoublerON.py". However output frequency is not 983 MHz, but 860 MHz. It looks like PLL2 is not locked, and the internal VCO is stuck at low frequency.

 

The condition is:
- Connected 122.882 MHz at CLKIN0_RFSYNC_P input
- GPIO1 LED (PLL1 Lock) turns on.
- GPIO2 LED (PLL2 Lock) is off.
- CLKOUT10 frequency is 860.173 MHz

 

I added FSM restart and PLL2 status readout at the end of SPI sequence. There were 24 (0x18) autotune errors in the readout . That is:

 

# restart

time.sleep(0.01) # wait for 10 ms

rd = hmc7044.read(0x0001)

hmc7044.write(0x0001, rd | 0x01) # restart dividers/FSMs

time.sleep(0.01) # wait for 10 ms

hmc7044.write(0x0001, rd) # negate restart bit

time.sleep(0.01) # wait for 10 ms

# show PLL2 status

hmc7044.read(0x008c) # PLL2 autotune value

hmc7044.read(0x008d) # PLL2 autotune error (LSB)

hmc7044.read(0x008e) # PLL2 autotune error (MSB)

hmc7044.read(0x008f) # PLL2 autotune FMS state

--->

 

debug: HMC7044 read(0x0001) --> 0x00
debug: HMC7044 write(0x0001, 0x01)
debug: HMC7044 write(0x0001, 0x00)
debug: HMC7044 read(0x008C) --> 0x1F
debug: HMC7044 read(0x008D) --> 0x18
debug: HMC7044 read(0x008E) --> 0x00
debug: HMC7044 read(0x008F) --> 0x00


Any ideas on fixing the issue?

Thank you,
--fuji

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