I am working with the interposer rev.A (schematic attached), the non_FMC AD9467 and the ZC706 FPGA: the DCO is connected to a simple FPGA IO pin (there isn't any physical line between a simple IO pin and any clock buffer).
I set the CLOCK_DEDICATED_ROUT property to false, I turned off an error compiling the design (see attached log file), but the portion of my system which the DCO clock had to use presented a big clock skew. And it's not working properly (see the attached figure).
1) I am wondering if the clock setting could be modified or there is no way to correct that. I believe that is crucial to use a clock dedicated IO to receive the DCO from the AD9467. If the clock window is modified, could be all channel data be synchronised?
2) Checking the schematic of the rev.B interposer, the A1/B1 is connected to G6/G7 of the FMC connector, which on the ZC706 is connected to IO_L14P_T2_SRCC_11/IO_L14N_T2_SRCC_11. Those pins are single region clock capable IO pins, good to receive external clock signals.
Could it be possible to bridge these two connections in my interposer? I would connect DCLK2CC+ (D20) DCLK2CC- (D21) to the G6 and G7 of my interposer Rev.A board. These two pins would be connected to a dedicated receive FPGA clock signal. Could this bridge be possible in terms of synchronisation and pitch length ?
3) I'm not too familiar with the non-FMC AD9467 and FMC AD9467 evaluation boards, could it be possible to know all the differences between both cards?
Thanks in advance