In FDD mode, D1 of register 0x016, doesn't self clear after RF DC Calibration.
But 0x017[7:4]==1, showing that all calibrations had succeeded.
In TDD mode, D1 of register 0x016, does self clear after RF DC Calibration.
Are you suing ADI provided API?
Is it a custom hardware?
Yeah, custom hardware and firmware. AD9364 was configured by FPGA through a SPI FSM designed by myself.
Rf dc calibration procedure: spiwrite 0x02 to 0x016; wait some time; spiread 0x016; check 0x016.
In tdd mode, everything is Ok.
But in fdd mode, 0x016 doesn't self clear. If the SPI FSM insist to check the self clear of 0x016, it would stucked at a deadlock of spiread and check. If FSM doesn't insist, everything is Ok, just as in tdd mode, and 0x017[7:4]==1.
Are you using ad9361_rf_dc_offset_calib() API from NO-OS?
If not refer the N0-OS API for other settings which you may be missing.
I didn't use the ad9361_rf_dc_offset_calib() API from NO-OS.
AD9364 was configured by FPGA through a SPI FSM designed by myself. The FSM plays the role of a application specific Reduced Instruction Set Computer.
The softwares of tdd&fdd configuration were translated from Init Scripts generated by AD936x Evaluation Software Version 2.1.1.
We recommend to use ADI provided drivers. You may be missing some sequence or config required in FDD state.
Retrieving data ...