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ADUM5401 and ADM3053: Question Regarding Board Layout to Reduce EMI

Question asked by b_rad on Sep 29, 2017
Latest reply on Oct 31, 2017 by James.Scanlon

Background:

  • We are using 3 ADUM5401 (RS485 serial) and 1 ADM3053 (CAN bus) to isolate 4 communication ports on a very compact (roughly 8 cm square) 4 layer circuit board with a DSP.
  • We are currently having trouble complying with the radiated EMI requirements of EN60945 when cables are connected to the communication ports. However, when the communication port cables are disconnected, we are well below the emission limits.  At this point I am not sure if this is related to lower current on the IsoPower circuits or because of the shielding effect of our enclosure or both.  Our biggest problems are at 358 MHz and 1073 MHz.  We are able to reduce the noise radiated from the cables by 4-8dBuV/m but only by using an unacceptably large number of high frequency and broadband ferrites.

 

I am now working on a re-layout of this circuit board to correct the issues.  I have read AN-0971 and AN-1349 and have the following questions:

 

In regard to Figure 1 in AN-1349 and its applicability to the ADM3053:

  • Assuming you have larger power and (“stitched”) ground planes in the circuit board layers below what is shown in this diagram, where should your vias be placed relative the capacitor and ferrite filtering components? Should they be right at the chip pins or should they be further away after the capacitors and ferrites in order to introduce a small amount of series inductance / resistance in some or all of these connections?
  • Can you please clarify or explain why most of the document examples show large power and ground planes extending out of the stitching overlap area and yet there is one line on page 3 of AN-1394 that says “To allow additional margin for passing emission limits, the GND2 plane area must be minimized.” So other than the stitching overlap zone, should we even have a GND2 plane?  Also please confirm that there should also be no positive power plane on the isolated side.

 

In regard to the ADUM5401 and AN-0917:

  • Again, where should vias to the power and ground plans be placed in relation to the filter capacitors?
  • Can the discrete stitching capacitor still be placed as close as possible to pins 8 and 9?
  • With the ADUM5401 should we still try to keep the isolated power and ground planes as small as possible outside the stitching area as described in AN-1349?

 

In regards to preventing the noise from leaving the circuit board on the signal lines which connect via plug in connectors and seem to act as antennas externally:

  • Do you have any experience or recommendations of the most effective ways to prevent this with these IsoPower circuits? 
  • Obviously feed through capacitors with the capacitor connected to our enclosure shield ground is the traditional method to deal with this but it would be useful to have further information on how this works in the real world with these Isopower chips and with signal lines connected to the isolated side of these circuits.
  • Any suggestions on the best parts and configuration to use for this application would be greatly appreciated.

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