Is there any way I can program a input of the eval board to an output of the eval board using the Register Window Builder Program. I would like to plug some PC audio to an input and then a speaker or headset to the output.
Thank you for your interest in the AD1937 codec.
The USBi control interface and Register Window Builder program are only able to control the registers in the AD1937; the routing of clock and data on the eval board are not affected by this control path.
I have two methods to complete a loop-through from ADC to DAC:
1) Connecting a coax cable from the SPDIF output to the SPDIF input; the signal at ADC pair 1 should appear at all DAC pair outputs.
2) Using short patch cords, connect the serial clock and data signals from the ADC output to the DAC input using the pins at HDR1.
The routing of clock and data through the CPLD on the board is described fully in the User Guide which is available on the AD1937 product page:
Please let me know if this is not clear or if other questions come up.
A question about AD1937, from the DS I find the ADCs and DACs use the same clock, right? if I wanna the ADCs and DACs use different clocks for input and output signals, how to realize it, can you help give some suggestion?
Many thanks for your help!
The AD1937 is very flexible so no, they do not have to use the same clocks or the same settings. You can even have them at different sampling frequencies. This can get a little complicated and I do not know the details of the system you are designing. So I will be a bit general with my reply.
If you are running on an overall system MCLK then you could have the ADC be the master to another part in your system, a DSP, and the DAC could be a slave off of the DSP. If everything is working from the same MCLK then it will all work.
Now, for some reason if the ADC data is going out to something that is not synchronized to the audio that is being sent to the DAC then you can run with the ADC or the DAC in direct MCLK mode. This is where one of the sections, let's say the ADC, will use the on-chip PLL for its clocks but the other section, the DACs, will use a different MCLK that is coherent with the BCLK and LRCLK that is being sent to the DAC.
This is setup in the "PLL and Clock Control 1 Register". So in my example, you could have the DAC clock source, bit-0 = 1, so the DAC will get its MCLK from the MCLKI pin and then set the ADC to take its MCLK from the PLL clock, bit1 = 0. Then in the "PLL and Clock Control 0 Register" you would set the PLL input to be ALRCLK, bits 6:5 = 0b10. This will take the LRCLK coming in on the ALRCLK pin and use that to drive the PLL. Then they can both be set to slave from incoming clocks for BCLK and LRCLK and do not have to be synchronous.
If you supply more details on what your clocking scheme is then I can be more specific.
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