When i use muthic ch,Which timing RDY singnal change
I think the first diagram is partially correct but might be confusing. So I think it might be worth it to change the timing as shown below. This is for a selected sinc 4 filter. The settling time for a sinc 4 filter requires 4 conversion cycles before the part become fully settled. This settling time plus the extra delay called dead time is allowed to generate the very first conversion after the channel change and the subsequent conversions on this channel will occur at the selected output data rate. RDY will go low when a conversion is complete, thus, it will go low after the very first conversion and every after the subsequent conversions on this channel. It might be also worth it to visit our Virtual Eval Tool that lets you play with the various features and see the performance of various ADCs online including the timing. You can check there the timing diagram for AD7124.
Kindly provide what particular product that you are referring to with this thread.
Sorry , my product is AD7124-4
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