1x Xilinx FPGA
We are setting up JESD channels to send data into the FPGA from the ADCs. We're able to establish sync in JESD subclass 1 but we'd like to shut SYSREF down after sync is established. I have a question about how SYSREF timer works.
As I understand it, each SYSREF period is the time allotted to each SYSREF channel to output SYSREF. So, if timer is set to 1MHz and channel dividers are set to produce a 30MHz sysref, then 30 cycles are produced per SYSREF period. And if Number Pulses = 2, then *90* cycles are produced because STARTUP state is a valid SYSREF output state, in addition to the 2 Pulse Generate states. Am I right so far?
We currently have our HMC programmed for:
Base frequency of 2.4GHz
CH2: Pulse Generator mode, Force Mute, Dynamic Driver enabled, LVDS (I realize that Force Mute has no bearing on LVDS mode). Channel Divider: 0x0050
SYSREF timer: 0x0960 (which is common multiple of our channel dividers of 0x0050, 0x0018 and 0x000C)
Pulse Generator Mode: Continuous (0x07)
My question is: While SYSREF is in continuous pulse generation mode, what happens if we disable SYSREF timer (Address: 0x033, Data: 0x33)? Does it just immediately shut off the SYSREF channels? Or will it continue generating SYSREF since we're in continuous mode? I'm not sure what happens from the flow diagram in the User Guide (attached below) since Pulse Generator never times out:
Is disabling SYSREF timer the preferred method of shutting down SYSREF, as opposed to shutting down the individual SYSREF channels.
We did try disabling SYSREF timer but it had no effect on SYSREF. So, we're wondering if it's a SPI issue (note: we do all of our programming via SPI initially so we have some confidence that our SPI controller is working) or if we should be disabling SYSREF by another method.
Thanks in advance.