For a dual 6-wire load cell application, 1-6 parallel cells per channel, I would like to use the AD7193 with 5V excitation, a minimal of 4SPS is required (fully settled).
For good 50/60Hz rejection the settings are: FS=96, SINC4, REJ60=1 and with a post filter of 8 averaged samples. The internal sequencer of the AD7193 can’t be used since the external reference needs to be switched.
I’m I correct in assuming that this results in 4-4.5SPS, and every sample is fully settled?
The sample rate will be a little slower than 4.5SPS due to the communication needed to switch the channel and reference after each conversion.
Due to space and cost constrains I don’t want to use a reference buffer. Also, because the buffers would need extra voltage rails.
For overvoltage protection and filtering, I would like to add 2x220R series resistance, 2x a CM cap of 10nF and a DM cap of 0.1-1uF from the sense lines to the reference pins of the AD7193.
This introduces a typical gain error of ~0.2% for 4.5uA/V reference current. This is acceptable since it can easily be calibrated out. When the loadcell is connected the cable resistance,<4R, introduces a gain error of 20 ppm, this is also acceptable.
An external clock will be used so the reference current drift is typically 30pA / V / dC. The extra introduced gain drift can be neglected in this application.
Although not specified it is assumed that the reference sampling capacitor is <20pF. The DM capacitor should minimize the charge distribution error to neglectable values also, this error is calibrated out.
Are there some additional errors that I missed?
For example, the INL or additional errors introduced by the switching of the reference capacitor.
Thanks in advance,