In our new project i would like to use two ADA2200 for dual channel IQ demodulation of LVDT transducer interface.
Attached is the basic schematic.
Could you pls send your feedback?
The circuit looks good, but one thing isn’t explicitly clear on your schematic. That is the clocking of the AD7124. A key requirement to getting the best noise performance from the system will be the synchronization of all of the clocks in the system. Do not use the internal clock of the AD7124. Instead drive the AD7124 CLK input from the FPGA.
There should be an integer relationship between the excitation frequency generated by the AD5592 and the input sampling rate of the ADA2200. So,
fSI_2200/f_EXC = 64*M, where M is an integer
Also, there should be an integer ratio between the output sampling rate of the AD7124 and the excitation frequency. So,
F_EXC/fS_7124 = N, where N is an integer. (You can think of the as each AD7124 output sample is the average value of the ADA2200 output averaged over N cycles of the excitation signal.)
Thank you so much.
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