I have completed my initial evaluation of your HDL and no-OS support for the Xilinx KCU105/FMCDAQ2 combination and it has gone well. I still have some questions that can be answered later, and I am also working with Analog Devices on the hdl/no-OS Xilinx ZCU102/FMCDAQ2 support which is not yet completely working yet.
My next step is to start using the Mathworks Matlab/Simulink HDL coder and Embedded Coder and begin inserting blocks into the hdl code that Analog Devices has created for the hdl/no-OS reference design.
Currently your no-OS fmcdaq2.c code is doing the following:
DAC Interface - The DAC data may be sourced from an internal data generator (DDS, pattern or PRBS) or from the external DDR via DMA. The internal DDS phase and frequency are programmable.
ADC Interface - The ADC data is sent to the DDR via DMA. The core also supports PN monitoring at the sample level. This is different from the JESD204B specific PN sequence (though they both claim to be from the same equation).
These are my questions:
My first step is to not transmit data from memory or use the DDS in the AD9144 as used in the no-OS example, but to rather use a custom Matlab block generating a waveform.
1) Where in the Vivado block diagram do I insert this block? Wouldn't it be somewhere in the AD9144 path?
2) Do you have an example Vivado project in github that I can open?
I have attached a photo of the Vivado 2016.2 fmcdaq2/kcu105 hdl and no-OS block diagrams. This is so you can see where I am trying to figure out where to insert my custom Matlab block.