Hi Support Team,
I am trying to use the EV-ADF4002SD1Z board to evaluate a PLL consisting of ADF4002+204.8MHz VCXO. I have the SDP-S board and am using the INT-N PLL Software (v7.7.4).
I am able to communicate with the SDP-S (can flash SDP LED via the GUI) and the log at the bottom of the GUI indicates that I am successfully writing registers. I am using the following write procedure (initialization latch -> function latch -> R latch -> N latch) however I am not seeing any signal at Cp and lock is not detected.
I have verified that there is a correct frequency/amplitude signal on REFIN and RFINA (feedback from the VCXO). Do you have any debug suggestions? Is the INT-N-PLL Software v7.7.4 compatible with this EVB, it seems pretty old.
The plan I would like to use has REFIN=10.24MHz. I noticed that this is below the recommended input frequency range but the slew rate on the reference clock is 3.6 kV/us, much greater than 50V/us.Is this a problem? I also tried using a REFIN of 20.48 MHz and 204.8 MHz, however still saw no output at Cp and lock not detected.