I have a question of the "cp_vid_std" register of ADV7480.
I saw the details of cp_vid_std on the H/W manual, page. 166 and 167.
The manual says :
"The picture gets shifted by equal number of clocks as the hsync width.
For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks.".
"This results in the following settings (the sequence of the writes is important and must be followed):
1. Set register 0x8B in the CP Map to value 0x43
2. Set register 0x8C in the CP Map to value 0xD8
3. Set register 0x8B in the CP Map to value 0x4F
4. Set register 0x8D in the CP Map to value 0xD8"
I can understand the above descriptions.
But I can not understand the following description:
"These adjustments do not affect the free run mode. But if the CP test pattern generator is used, these writes will affect it, i.e. they will shift incorrectly the test pattern generated internally by the CP core.
So if the CP test pattern generator gets enabled, de_h_end[9:0] and de_h_start[9:0] shall be set back to their default values while the pattern generator is enabled."
In free run mode, do you mean there is no method which these adjustments settings can be affected?
The second sentence "But if the CP test pattern generator is used, these writes will affect it" confuses me.
I think the CP test pattern generator must be used in free run mode.