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how to add memory register(ad_cpu_interconnect) to own HDL in picozed sdr som

Question asked by Aban on Sep 22, 2017
Latest reply on Sep 26, 2017 by Aban

Hi

 

We have a picozed-sdr-som board with 3 AD9361 connected to it(one  of AD9361 is in the board itself). The  linux Image (from analog devices) running and I am able to stream data to one AD9361 via ad9361_iiostream.c application(we modified the example program) , and oscilloscope application.

 

In the FPGA we added our own module multi_channel_sync which takes 2 RX channels from 2 of AD9361s , adds them and sends the results on 2 TX channel of the 3rd AD9361.  This setup is synthesizing and running for us.  Now we want to add a AXI interface to it , so we can control it by writing to a memory address (ie, a memory register). 

I added ad_cpu_interconnect and defined the s_axi_* signals in the multi_channel_sync.v module interface. However I am getting errors below on synthesizing.

 

create_bd_cell -type module -reference multi_channel_sync -name multi_channel_sync -quiet

 

connect_bd_net -net [get_bd_net /axi_ad9361_clk] [get_bd_pins multi_channel_sync/clk]
connect_bd_net -net [get_bd_net /fmcomms2_rst] [get_bd_pins multi_channel_sync/rst]

 

ad_cpu_interconnect 0x79080000 multi_channel_sync

 

ERRORS:

### ad_cpu_interconnect 0x79080000 multi_channel_sync
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK
connect_bd_net -net /sys_cpu_clk /multi_channel_sync/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN
connect_bd_net -net /sys_cpu_resetn /multi_channel_sync/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /multi_channel_sync/s_axi
ERROR: [BD 41-1075] Cannot create address segment for </multi_channel_sync/s_axi/reg0> in </sys_ps7/Data> at 0x079080000 [ 4G ]. The proposed address exceeds the base address limitations <0x40000000 [ 1G ]> of the interface(s) </sys_ps7/M_AXI_GP0> through which this peripheral is accessed by this address space
ERROR: [BD 5-14] Error: running create_bd_segment.
ERROR: [Common 17-39] 'create_bd_addr_seg' failed due to earlier errors.

while executing

 

Can you please help. Is it because of create_bd_cell -type module ? For axi_ad9361 it was created as -type ip , and ad_cpu_interconnect worked. They use address 0x79020000, 0x79040000, 0x79060000, so this address is unused. Another side question is Can I somehow connect the cpu_interconnect signals to one of AXI_AD9361 to my HDL module. I can then use the unutilized register space to control my module.

 

Here is the connections for my HDL in my /projects/pzdsdr2/bolton/pzdr_bolton.tcl

connect_bd_net [get_bd_pins axi_ad9361/adc_valid_i0]    [get_bd_pins multi_channel_sync/adc_valid_i0]
connect_bd_net [get_bd_pins axi_ad9361/adc_data_i0]     [get_bd_pins multi_channel_sync/adc_data_i0]
connect_bd_net [get_bd_pins axi_ad9361/adc_valid_q0]    [get_bd_pins multi_channel_sync/adc_valid_q0]
connect_bd_net [get_bd_pins axi_ad9361/adc_data_q0]     [get_bd_pins multi_channel_sync/adc_data_q0]
connect_bd_net [get_bd_pins axi_ad9361/adc_valid_i1]    [get_bd_pins multi_channel_sync/adc_valid_i1]
connect_bd_net [get_bd_pins axi_ad9361/adc_data_i1]     [get_bd_pins multi_channel_sync/adc_data_i1]
connect_bd_net [get_bd_pins axi_ad9361/adc_valid_q1]    [get_bd_pins multi_channel_sync/adc_valid_q1]
connect_bd_net [get_bd_pins axi_ad9361/adc_data_q1]     [get_bd_pins multi_channel_sync/adc_data_q1]

 

connect_bd_net [get_bd_pins som2_axi_ad9361/adc_valid_i0]       [get_bd_pins multi_channel_sync/adc_valid_i2]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_data_i0]        [get_bd_pins multi_channel_sync/adc_data_i2]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_valid_q0]       [get_bd_pins multi_channel_sync/adc_valid_q2]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_data_q0]        [get_bd_pins multi_channel_sync/adc_data_q2]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_valid_i1]       [get_bd_pins multi_channel_sync/adc_valid_i3]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_data_i1]        [get_bd_pins multi_channel_sync/adc_data_i3]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_valid_q1]       [get_bd_pins multi_channel_sync/adc_valid_q3]
connect_bd_net [get_bd_pins som2_axi_ad9361/adc_data_q1]        [get_bd_pins multi_channel_sync/adc_data_q3]

 


connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_valid_i0]  [get_bd_pins multi_channel_sync/dac_valid_i0]
connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_valid_q0]  [get_bd_pins multi_channel_sync/dac_valid_q0]
connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_valid_i1]  [get_bd_pins multi_channel_sync/dac_valid_i1]
connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_data_i1 ]  [get_bd_pins multi_channel_sync/dac_data_i1]
connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_valid_q1]  [get_bd_pins multi_channel_sync/dac_valid_q1]
connect_bd_net  [get_bd_pins fmcomms2_axi_ad9361/dac_data_q1 ]  [get_bd_pins multi_channel_sync/dac_data_q1]
larsc                                                               

Outcomes