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AD9680-500 JESD PLL not locking

Question asked by skillers on Sep 22, 2017
Latest reply on Sep 27, 2017 by skillers

I have an AD9680-500 device but are having issues getting it to work, in particular the JESD link. I am able to communicate with the device over SPI, but cannot getting a working JESD connecion. WHen checking the status bits, the error appears to be with the JESD PLL not locking.

My initialisation procedure sets the following registers in this order over SPI (where mask is bitmask where other bits are read and left unchanged when writing back):
Register, value, mask
0x5B0, 0x00, 0x55 - disable all lane powers
0x571, 0x01, 0x01 - disable JESD link power
0x570, 0x49, 0xFF - JESD quick configuration setting
0x201, 0x00, 0x07 - Chip decimation setting (1 - have also tried setting 0x01 for a decimation setting of 2)
0x58F, 0x8F, 0xDF - 2 control bits and 14 ADC bits per sample.
0x559, 0x11, 0x77 - Setting control bits to overrange.
0x55A, 0x01, 0x07 - Setting control bits to overrange.
0x56E, 0x00, 0x10 - High line rate (set to 0x10 when decimation is 2)
0x590, 0x00, 0x20 - JESD subclass = 0 (have also tried 1)

0x5B0, 0x05, 0x55 - enable 0+1 lane powers
0x571, 0x00, 0x01 - enable JESD link power

After this (and before) when reading 0x11C I get 0x01 - clock is detected, but 0x56F gives 0x00 - no PLL lock.
The clock signal is a 500 MHz differential sine like wave with pk-pk of ~1.2V.

I have also tried different combinations 

Is there something I am missing or a setting that I am doing wrong?

Also, as an aside, does the chip decimation setting apply to even ADC sampling, so could be used to output 250 MSPS on each adc while running at 500 MHz? This would make it easier to test as I have a known working 250 MSPS device and JESD receiver and as such would only be modifying the adc and not the JESD receiver in the initial stage of testing.