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Question about interrupt latency

Question asked by BNewhall on Sep 21, 2017
Latest reply on Oct 9, 2017 by BNewhall


I have a question regarding the IRQ0_N interrupt on the ADSP-21479BSWZ-2A.

I have the interrupt configured to be edge sensitive and at the start of the interrupt service routine I set FLAG3 high. The SHARC is running at 260MHz core clock speed, so I am expecting around 30 nanoseconds delay between the falling edge of the FLAG0 pin and the rising edge of FLAG3. I’m expecting the 30 nanoseconds based of the datasheet stating that all interrupt requests are acknowledged with up to fPCLK/4 speed.

When measuring the time between the two signals with an oscilloscope I see the time between the falling edge of the FLAG0 pin and the rising edge of the FLAG3 pin to be about 600 nanoseconds.

I was wondering if there is some information that I am missing or misinterpreting that could explain the delay between receiving the interrupt signal and acting on it, thank you for your help.



I am using the built in interrupt installer that comes with cross core

adi_int_InstallHandler(ADI_CID_IRQ0I, (ADI_INT_HANDLER_PTR) IRQ0_isr, NULL, true);

Interrupt routine:

void IRQ0_isr(uint32_t iid, void* handlerArg)


   sysreg_bit_set(sysreg_FLAGS, FLG3);


     My interrupt routine


   sysreg_bit_clr(sysreg_FLAGS, FLG3);