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Configuration of AD9361 in TDD mode

Question asked by Soap on Sep 20, 2017
Latest reply on Sep 22, 2017 by Soap

Hi all, I am confused in calculating DATA speed of AD9361 in TDD mode.

 

  1. I want AD9361 to work at TDD mode, so it's configured as DDR + dual port + half duplex + CMOS.    As is shown above,  can I conclude that the speed of R1(including R1_I,R1_Q) is twice as that of DATA_CLK?
  2. Suppose 1 is right, I set DATA_CLK as 1.92M, and inner filters are configured rightly to get a 1.4M bandwidth, but the speed of RX_DATA(after all these filters) is 3.84M? Something must be wrong!

 

 

 

3. To switch between TX and RX, the ENSM must be in ALERT state, but how to know ENSM state quickly? I am using FPGA, so reading SPI register is not easy.

4. ENSM is controlled by the TXNRX and ENABLE pin(Figure 11), how many FB_CLKs will it take to change from RX to TX? Can the time be shortened?

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