I am using the 2016_R1 stable releases of 'hdl' and 'no-OS' for my KC705 board (rev 1.1) combined with an AD-FMCOMMS1-EBZ (rev C).
When using the GUI mode of Vivado 2015.4.2, the synthesis is successful, but the implementation stage fails because of not met timing constraints (negative slacks).
However when compiling the HDL project with the 'make' command in Cygwin the implementation goes well along (positive slacks).
How come that difference? What is the workaround please?
I would like to use the Vivado GUI for setting-up for Debug...and still meet the timing constraints..
PS My configuration: Vivado 2015.4.2 64 bits, on Windows 7 64 bits, 16GB of RAM