we are using an AD9653 dc-coupled with an ADA4930 as a single-ended to differential converter on a custom board. The ADC is interfaced with an Altera Cyclone V evaluation board. We can capture in a correct way the test patterns on the DDR interface, so I suppose that the link ADC-FPGA is stable and works.
The sample clock is running at 50 MHz, Vref is external and supplied by the ADR130.
When we capture a real signal (for example a square wave), we observe a series of random spikes (in the same way for each channel): it seems that the amplitude of these spikes is always the real signal plus or minus 256 (the 8th bit).
The encode clock is supplied by a programmable oscillator in LVDS format (LMK61E2): at the startup, the ADC is resetted via SPI as stated in the datasheet, to be sure that is properly initialized.
Is there the possibility that the ADC is not correctly configured via SPI?
Any idea will be greatly appreciated!