I am working on a new design using AD9136 and FPGA parts.
The DAC rate is 2.12 GS/s and the JESD204 lane rate is 10.6 Gbps.
Currently there are communication errors (Re-SYNC) over the JESD204. So I am trying to run datapath PRBS tests. Looking at the AD9135/AD9136 datasheet, it is described as "The datapath PRBS test is designed to support input data rates of up to 1060 MHz" in the page 69. However 1060 MHz is much slower than the max lane rate of 12.4 Gbps.
Is it correct?
I need to run PRBS test at 10.6 Gbps.
Any help would be appreciated.