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Question asked by cerasic on Sep 19, 2017
Latest reply on Oct 5, 2017 by CsomI
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Dear support,


I'm using the FMCDAQ2 ref design R2017_R1 in (ADC sampling 300Mhz, and DAC 1000Mhz), I get it working in DDS mode, but not Sine LUT. I tried to drive the TX path from DDR data, it didn't work also. When I replace the DMA and the DACFIFO by those from R2016_R2, it works for both cases Sine LUT and DDR data.

Firstly I replaced just the DMA R2017_R1 by DMA R2016_R2, I saw that right data coming out of the DACFIFO

and the size of the FIFO is 8192 samples. Then I tried to resize the DACFIFO increasing it to 128K samples, it was not possible, when I looked to the Verilog code of the DACFIFO, I saw a code grey function applied to the address, an this function is fixed to 10 bit which means 2^10 * 8 samples of data bus = 8192, so I decided to use the DACFIFO of R2016_R2, by doing this, every thing works better, DDS, Sine LUT, and also custom data in the DDR.

In summary, it seems that DMA R2017_R1 doesn't work well in TX path, and the DACFIFO is not resizable.

Please can you confirm that and advice me how to fix that (if I have to use only R2017_R1).

Thanks a lot for your help