Our customer will use ADXL372 at external sync (2000Hz) and internal clock (ODR=3200 Hz setting).
Datasheet rev.0 P24 "SYNCHRONIZED DATA SAMPLING" says below.
The EXT_SYNC is an active high signal. Due to the asynchronous
nature of the internal clock and external sync, there may be a
one ODR clock cycle difference between consecutive external sync
What does one ODR clock cycle difference mean ?
I think that ADXL372 outputs date at 1/3200 second after sync (every 1/2000 second )
when SYNC is 2000Hz and ODR setting is3200Hz (internal clock ).
Please let me know your advice how "one ODR clock cycle difference" affects ADXL372 operation .