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AD9956 fractional divider - waveform quality

Question asked by rf_rookie on Sep 17, 2017
Latest reply on Sep 19, 2017 by mcee

I read some old posts about setting up a fractional divider loop with AD9956, though I still don’t get it. My question comes, how pure does the sine wave output (J6) should be? I tested my DDS in an open loop configuration without connecting it to the Phase frequency detector and using an external function generator @2400 MHz (vco is not feeding the system). The DDS waveform output (J6) at 25 MHz, close enough to my PLL ref, is distorted. How much does a distorted waveform, connected to the PLLOSC, affects the PLL performance?

In order to check that my locking system is working properly, do I need to monitor and control the function registers directly? Or Is the ADD956 software enough?

These are my setting:

Ref. Clock 2400 MHz

Divider Ratio: 8

System clock: 312.5 MHz

PLL ref: 25MHz

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