When debugging SPI, BBPLL debugging is normal, but RX / TX CP CAL read the data is ox68, no lock, and RX / TX PLL is not locked.like these:
1.What are the cause of the problem?
2.How do I find the problem?
3.how to solve this problem?
Which SW driver are you using, Linux or NO-OS ?
Can you share more details on your hardware , it an Evaluation platform or custom board. ?
Thank you for your reply.Using the FPGA chip is xilinx V6 series chip; I use Verilog write SPI configuration program, but the register configuration all in accordance with the BBS.TXT inside the configuration.
I found a bug in my program yesterday, after change， the results like these：
Thanks for the update. \
We will not be able to support on direct register writes.
Retrieving data ...