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Timing Constraints in Reference Design MathWorks HDL Workflow Advisor FMCOMMS3/5

Question asked by SoerenS on Sep 15, 2017
Latest reply on Oct 5, 2017 by rejeesh

Hi,

 

I am trying to create a custom HDL tx design for the FMCOMMS 3 or FMCOMMS 5. (I have both on a zc706)

I got the MathWorks tools (master branch) working with Matlab 2016b and Vivado 2015.2.

My own design is synthesised, but when I opened the design in Vivado, I noticed some timing problems.

 

By trying to debug, I saw, that some contraints don't work.

WARNING: [Vivado 12-180] No cells matched 'ddata_reg*'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:139]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_cells -hier ddata_reg* -filter {primitive_subgroup == flop}]'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:139]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'enable_cnt*_reg*'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:143]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_cells -hier enable_cnt*_reg* -filter {primitive_subgroup == flop}]'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:143]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier *_counter_reg* -filter {name =~ *util_upack_dac* && primitive_subgroup == flop}'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:149]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_cells -hier *_counter_reg* -filter {name =~ *util_upack_dac* && primitive_subgroup == flop}]'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:149]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'dac_enable_d1_reg*'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:153]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_cells -hier dac_enable_d1_reg* -filter {name =~ *util_upack_dac* && primitive_subgroup == flop}]'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:153]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier dma_rd_reg* -filter {name =~ *util_upack_dac* && primitive_subgroup == flop}'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:157]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_cells -hier dma_rd_reg* -filter {name =~ *util_upack_dac* && primitive_subgroup == flop}]'. [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc:157]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/fmcomms5/zc706/system_constr.xdc]
Parsing XDC File [H:/analogDevices/simulink_fmcomms_test_2016b/hdl_prj/vivado_ip_prj/projects/common/zc706/zc706_system_constr.xdc]

 

To get the FMCOMMS 5 synthesis running, I had to resolve some problems in the MathWorks tools.

It seems, that the hdl reference is updated from hdl_2014_r2 to hdl_2015_r2 and the design of the unpack ip core is changed. I changed the interface connections (in the matlab package) for the new unpack block.

The FMCOMMS 3 had the new port names by default.

 

When I look deeper into the timing analysis, I see a lot of the timing violations are related to the new unpack core. In the "system_constr.xdc" file are some contraints related to the old unpack implementation.

# timing rx

set_false_path \
    -from [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
    -to [get_cells -hier ddata_reg* -filter {primitive_subgroup == flop}]

set_false_path \
    -from [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
    -to [get_cells -hier enable_cnt*_reg* -filter {primitive_subgroup == flop}]

# timing tx
    
set_false_path \
    -from [get_cells -hier dac_enable_reg* -filter {primitive_subgroup == flop}] \
    -to [get_cells -hier *_counter_reg* -filter {name =~ *util_dac_unpack* && primitive_subgroup == flop}]

set_false_path \
    -from [get_cells -hier dac_enable_reg* -filter {primitive_subgroup == flop}] \
    -to [get_cells -hier dac_enable_d1_reg* -filter {name =~ *util_dac_unpack* && primitive_subgroup == flop}]

set_false_path \
    -from [get_cells -hier dac_enable_reg* -filter {primitive_subgroup == flop}] \
    -to [get_cells -hier dma_rd_reg* -filter {name =~ *util_dac_unpack* && primitive_subgroup == flop}]         

I attached the time report to this post.

 

Can you advise to fix the timing with the unpack core of hdl_2015_r2?

 

Many thanks in advance

Soeren

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