I want to use adsp21489 PCGS to generate TDM 8 channels clock for codecs(PCM4104).. And I config the PCG get correct clock output, MCLK-12.288M ,SCLK-12.2888M, LRCLK-48K. the clock wave looks like this:
Yellow clock: LRCLK
BLUE clock: SCLK
But the CODEC datasheet require clock is, So I need to change PCG get the following output , it means LRCLK rising , SCLK falling. and LRCLK falling, SCLK also falling .....
1..How to config PCG get this output..I'll put my some piece of PCG's code,!!
2..also I notice with PCG_CTLA0 and PCG_CTLA1 have FSxPHASE bits, but whatever how I try it , the output always the same .. So whats the meaning of FSxPHASE_LO and FSxPHASE_HI?
int n,r0 ;
*pPCG_CTLA1 =0 ; *pPCG_CTLA0 =0;
for (n=0; n<16; n++)asm("NOP;");
//*pPCG_PW2 = STROBEA| INVFSA;
r0 = sclk_div | CLKASOURCE | FSASOURCE;
*pPCG_CTLA1 = r0 ;
r0 = fs_div | ENFSA | ENCLKA;
*pPCG_CTLA0 = r0;