I have a 4DSP FMC104 ADC card that uses an AD9510 PLL with a VCO that tunes over 1150 to 1310 MHz. I have configured the PLL for CLK2 input form the VCO operate the VCO at 1200MHz with all output dividers set for 8 to achieve a 150MHz clock. I have used ADSim to model the loop given the on-card loop filter components at an Icp of 4.8mA. The simulation gives a loop BW of 10kHz and a phase margin of 45 deg. The simulation looks good to me but I could be missing something?
Two sample systems seem to operate fine over many weeks of continuous testing. However, others show the clock go unstable and disappear for tens of microseconds before reappearing. This behavior may only happen once in a day or two.
This does not appear to be a loss-of-lock but condition because the output frequency does not drift, it just stops for a period of time and returns. Is it true that a loss of lock or input reference would NOT cause the output clock to go away but rather it would simply allow the VCO to drift in frequency?
I have proved that the input reference signal (100MHz divided to 10MHZ for Fpfd) and input power are stable when the anomaly occurs. However, I have not been able to actually monitor the digital lock detector output from the output multiplexer due to a design restriction that uses the MUXOUT pin in tri-state to keep the internal reference enabled.
If the problem could be caused by a loss-of-lock then what possible remedies do I have. Is there any other way to monitor loss-of-lock without using the STATUS pin?
I have just tried one PLL configuration change that may help - but I am not sure? The change is to set the anti-backlash pulse width from the 1.3ns default to 6ns. I am not sure that this change could help but thought it is worth a try.
Can anyone help guide me to help isolate the problem? Could I simply have made a configuration error?
I have attached the .C file that sends the SPI configuration words starting at line 113.