I am using AD-FMCJESDADC1-EBZ (ADI) an KC705 to learn JESD204B. I am using the vivado to do this .. As i konw, the JESD204B rx ip core need three clock : core clock for The JESD204 core ;Reference Clock for The GTP/GTX/GTH; AXI4-Lite Interface Clock. core clock is generated by ad9517, Reference Clock and AXI4-Lite Interface Clock is supply by KC705. When I implement the design，it show the error below . I am very sorry for the photos. could anyone help for the problem.