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AD9361 setup NoOS

Question asked by thor@so-logic.net on Sep 14, 2017
Latest reply on Nov 15, 2017 by DragosB

We have looked at the references No-OS Software and No-OS Setup of the AD9361 and we still need a help.
Could you give me the command sequence for:
1. Setting it in FDD mode;
From power on, what´s AD9361 blocks we should turn on and leave (or force) off if we´re not going to use the auxiliary AD and DA´s, radioSW, TxMon and the reference oscillator;
2. Setting it in 1R1T mode;

3. Programming 8 frequencies for TX and 8 for RX;
We actually need 13 calibrated frequencies. How to calibrate them and save / store in BBP memory? How to swap a set of 8 of them to the cal register to have a fast frequency change?
4. Starting with an external clock at the input of the DCXO of 25 MHz, setting the baseband frequency to 976,5625 MHz, or multiplying the 25 MHz by 39,0625;
This is the only BBP frequency we´ll use. Any tip on this?
5. Setting the divider from baseband frequency to the ADC by 2 for obtaining 488.28125 MHz;
Any problem or tip for these frequencies (questions 5 to 9)?
6. Setting the divider from ADC clock to DAC clock by 2 for obtaining 244,140625 MHz;
7. Setting the divider from ADC clock to port clock by 8 for obtaining 61,03515625 MHz;
8. Setting the RX port for continuously outputting 12 bit I and Q data at 61,03515625 MHz;
9. Setting the TX port for continuously reading 12 bit I and Q data at 61,03515625 MHz;
10. Turning of the AGC function;
We´re going to use constant gain mode, and adjust it as needed (as a feedback after processing). Probably we´ll have some saturation during this process. How to get alarms from AD9361 on saturation in internal blocks?
11. Setting the gain of the LNA to a given and constant value;
This is for the feedback control on previous question.
12. Setting the gain of the mixers to a given and constant value of both I and Q channels;
Same as above
13. Setting the TIA to a cut-off frequency of 62.5 MHz and a given and constant gain of both I and Q channels;
Here we need help (or to check our understanding of your SW) on how to set TIA block and a way to set the gain (we´ll use this gain to adjust total channel gain);
14. Setting the Filter to a cut-off frequency of 35 MHz and a given and constant gain of both I and Q channels;
Same as above
15. Setting HB3=2, HB2=2, HB1=2, FIR=1 and GAIN to a given and constant value at the RX decimation digital filtering and equalization of both I and Q channels;
16. Setting HB3=2, HB2=2, HB1=1, FIR=1 at the Tx interpolation digital filtering and equalization of both I and Q channels;
17. Setting the first analog filter after the I and Q DACs at 32 MHz;
18. Setting the second analog filter after the I and Q DACs at 100 MHz;
19. We intend to use the “1” value at the DACs for the calibration process. How should be this “1” value? In both I and Q DACs or “1” for the I-DAC and “0” for the Q-DAC? The “1” should be the LSB, the MSB or a bit between LSB and MSB?
20. What frequency offset between Tx and Rx frequencies you recommend for calibration?
During Rx channels calibration, AD9361 needs an input signal. We intend to use the Tx channel LO to generate this signal as in question 19 above, and use our HW loopback function to put this tone back to the receiver port. Is there a better offset frequency to set in Tx to calibrate RX converters and filters to the configuration described (analog BW of 50 MHz – filters in 62.5 MHz – and I and Q filters in 35 MHz)?
21. After setting the optimum “1” for the DACs and the offset frequency, how should we proceed for starting the calibration?
Is there a need to calibrate the whole converter to all 13 frequencies in 3 bands?
22. After the calibration is done, how can we save all Tx and Rx settings to a certain register of the 8 available?
And how to save them to the BBP memory?
23. After all 8 frequencies parameters are saved, how we choose one of them and set the AD9361 for taking over it?
We´ll need a fast switch between frequencies, so we´d like to use the existing external controls to that. As far as the calibration register bank has place for 8 frequencies, we intend to swap the fast switch calibration registers with a copy of them in the BBP memory. Maybe it will be better to have all 13 frequencies calibration data in BBP memory and copy 8 of them at a time to the fast switch register bank.
24. How we start the 9361 for starting and stopping in FDD mode?

Any tip to do that to save time at startup?
25. For how often should we stop the FDD mode and start a calibration?
We´ll use the AD9361 for a while (~15 minutes) in continuous mode, switching all programmed frequencies transmitting and receiving. Then we´ll have a break to restart data collecting. Is there a need for calibration after such a working time? Is there any parameter that we can use to know that another calibration is needed (elapsed time from last calibration, temperature change, etc…)?

26. Are the mixer and BB parameters stored with LO parameters for fast band switching?

27. After transmitter pulse, we´d like to have transmitter output in off state (due to noise at output). Does BBprocessor take care of that without SPI control?

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