I had a hopefully quick question about using the AD916x series DACs in their FIR85/2x interpolation mode. Let me start by saying I am certainly not an expert in this space, I am merely trying to understand the practical limits of these devices and evaluation tools. So, to that end sentence 4 in the AD9161/2 datasheet says these devices can be used for Direct RF synthesis from DC to 6 GHz in 2x nonreturn-to-zero (NRZ) mode, which I am trying to understand a little better.
First let me cover what I do understand and please correct me where I am wrong. As we all know, the 8 lane JESD204B interface can only deliver a maximum of 12.5GBPS data to the AD916x which means the DAC itself is really only capable of clocking out unique 16bit samples at 5GSPS with overhead. (At least that is the maximum fdac ACE allows for, so I am not even sure where the datasheet's frequently referenced 6GSPS comes from, but I digress). Now, the DAC core itself can actually update its RF output at twice that speed in the FIR85 interpolation mode by sending updates out on both the rising and falling edge of its clock to reach a sort of 12GSPS speed (one real update and one internally interpolated update) which is more the number that AD seems to be marking. However, I still don't quite follow how that would translate into a true DC to 6GHz synthesis range that the datasheet seems to list. Let me explain:
In a prior Engineering Zone question here (https://ez.analog.com/thread/90051) someone else asked what the differences would be between the AD916x running the FIR85 and a true 12GSPS DAC. The generally accepted answer, which surprised me, was essentially there is little difference. But how can that be? Figure 162 in the AD9161/2 datasheet shows the output filter bandwidths for the bypass, FIR85, and other modes of the AS916x chips. Bypass mode offers DC to ~2.5GHz for example, as we would expect. If you look at the FIR85 mode the output bandwidth is now centered around 0Hz as that is a complex filter in the AD916x series. Ok, so let's say we simply use the NCO to shift our center frequency up to 1.25GHz to make the FIR85 output all real. But then the FIR85 bandwidth will still only cover roughly DC to 3GHz, even with this 12GSPS oversampling FIR85 on the output. Right?
So what am I missing? How is it possible to realize the datasheet claims of either 6GSPS "real" D-to-A output speeds or that this device has an actual real-time synthesis bandwidth of DC to 6GHz as the datasheet clearly (at least in my read of it) seems to imply right at the start?
Please let me know what I am misunderstanding.
Thanks in advance for any insights you can offer!