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FMCDAQ2 received data too noisy

Question asked by xsun on Sep 13, 2017
Latest reply on Sep 19, 2017 by rejeesh

Dear All,


I am now working on a project using FMCDAQ2. I have my own data source generator connected to the interface and capture the data which was transmitted over a short cable. I connect the output ports of the AD-FMCDAQ2-EBZ FMC module directly with coax cables to the input ports. The data coming out from my data source is a BPSK signal. At the transmitter, the data is captured by ILA show this:

Zoom in:

Binary sequence (0's & 1's) is mapped to -1('b1100000000000000) or 1('b0011111111111111). 

After transmission, at the receiver side, another ILA is used to capture the data:

Since the binary sequence is transmitted within the FPGA, there is a delay for the received noisy data, which is as expected. However, the received data is just too noisy... I do let my data source transmit 2048 zero's before the BPSK sequence to see the noise level. I can see very low noise before my BPSK sequence start and after. The noise level is very low. Only the last three bits were disturbed.

I expect the received BPSK sequence to be much nicer than this noisy fluctuate data. Right now, I am using the hdl_2016_r2 with an constraintfix patch. (see previous post: Add custom IP for data generation FMCDAQ2 )

My question is:

What is the mapping between ADC and DAC? DAC has 16 bits resolution while ADC has 14 bits.

What will be the corresponding value if 'b0011111111111111 or 'b1100000000000000 was transmitted?

I assume there will be no attenuation since I only use a very short cable to connect input and output ports.

From my receiver, only 8 bits have value.

What else will cause the received data to be that noisy?

Thank you very much.