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Extra vertical lines in ADV7181D active video output?

Question asked by icecream1 on Sep 13, 2017
Latest reply on Sep 14, 2017 by icecream1

I have a custom board that uses an ADV7181D to convert from NTSC video into BT656 (8 bit).  This data stream is then processed by an FPGA (cropped and scaled down) and output in CameraLink video format.  We are only using the Ybus output and the LLC clock between the decoder and the FPGA. The final CameraLink output video looks correct, with the exception of the fact that there seems to be a few extra vertical lines inserted in the image. It looks to me like a shift, as in extraneous data being inserted somewhere, rather than an overwriting of valid video data.


I've instrumented my FPGA design and I can see that these extra bytes are coming from the decoder in the datastream.  It seems like it must be a register setting of some kind in the decoder that I just don't understand.  I have two cameras that I have worked with; on one camera, there appear to be a few extra vertical lines at the left side of the image, and a few at the right side.  With the other camera, there are always 10 extra lines at the left side of the image.  These lines come in the datastream following the 0xFF | 0x00 |0x00 | SAV code, so I know the data is coming from the decoder and not something my FPGA has introduced.  What could cause extra bytes to be inserted into the active video?


This is the configuration I use to set up the ADV7181D:


        adv7181C_reg_write(0x00, 0x0B); //CVBS IN 
        adv7181C_reg_write(0x03, 0x0C); //8-Bit Mode
        adv7181C_reg_write(0x04, 0xF7); //Enable SFL, setting bit 7 so that BT656-4 is enabled...

        adv7181C_reg_write(0x13, 0x04); //Enable Oscillator /
        adv7181C_reg_write(0x17, 0x41); //Select SH1
        adv7181C_reg_write(0x1D, 0x47); //Enable 28MHz Crystal

        //using values from Table 22 in ADV7181D datasheet: Recommended user settings for NTSC
        adv7181C_reg_write(0x31, 0x1A); //Vsync field control 1
        adv7181C_reg_write(0x32, 0x81); //Vsync field control 2
        adv7181C_reg_write(0x33, 0x84); //Vsync field control 3
        adv7181C_reg_write(0x34, 0x00); //Hsync pos control 1
        adv7181C_reg_write(0x35, 0x00); //Hsync pos control 2
        adv7181C_reg_write(0x36, 0x7D); //Hsync pos control 3
        adv7181C_reg_write(0x37, 0xA1); //Hsync pos control 1

        adv7181C_reg_write(0x3A, 0x17); //Set Latch Clock & power down ADC 1 & ADC2 & ADC3
        adv7181C_reg_write(0x3B, 0x81); //Enable internal Bias
        adv7181C_reg_write(0x3D, 0x23); //MWE Enable Manual Window, Colour Kill Threshold to 2

        adv7181C_reg_write(0x86, 0x0B); //Enable stdi_line_count_mode
        adv7181C_reg_write(0xF3, 0x01); //Enable Anti Alias Filter on ADC0
        adv7181C_reg_write(0xF9, 0x03); //Set max v lock range
        adv7181C_reg_write(0x0E, 0x20); // ADI Recommended Setting
        adv7181C_reg_write(0x52, 0x46); // ADI Recommended Setting
        adv7181C_reg_write(0x54, 0x00); // ADI Recommended Setting 

        adv7181C_reg_write(0x7F, 0xFF); // ADI Recommended Setting
        adv7181C_reg_write(0x81, 0x30); // ADI Recommended Setting
        adv7181C_reg_write(0x90, 0xC9); // ADI Recommended Setting
        adv7181C_reg_write(0x91, 0x40); // ADI Recommended Setting
        adv7181C_reg_write(0x92, 0x3C); // ADI Recommended Setting
        adv7181C_reg_write(0x93, 0xCA); // ADI Recommended Setting
        adv7181C_reg_write(0x94, 0xD5); // ADI Recommended Setting
        adv7181C_reg_write(0xB1, 0xFF); // ADI Recommended Setting
        adv7181C_reg_write(0xB6, 0x08); // ADI Recommended Setting
        adv7181C_reg_write(0xC0, 0x9A); // ADI Recommended Setting
        adv7181C_reg_write(0xCF, 0x50); // ADI Recommended Setting
        adv7181C_reg_write(0xD0, 0x4E); // ADI Recommended Setting
        adv7181C_reg_write(0xD1, 0xB9); // ADI Recommended Setting
        adv7181C_reg_write(0xD6, 0xDD); // ADI Recommended Setting
        adv7181C_reg_write(0xD7, 0xE2); // ADI Recommended Setting

        //using values from Table 22 in ADV7181D datasheet: Recommended user settings for NTSC
        adv7181C_reg_write(0xE5, 0x41); // NTSC V Bit Begin
        adv7181C_reg_write(0xE6, 0x84); // NTSC V Bit END
        adv7181C_reg_write(0xE7, 0x06); // NTSC V Bit tog

        adv7181C_reg_write(0xF6, 0x3B); // ADI Recommended Setting
        adv7181C_reg_write(0x0E, 0x00); // ADI Recommended Setting