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BF527, problem with simultaneous operation of PPI DMA and SPORT DMA.

Question asked by ASergej on Sep 13, 2017
Latest reply on Sep 20, 2017 by Jithul_Janardhanan

Hi!

I have a custom board with BF527, 32 Mb SDRAM, RGB LCD (via PPI) and ADC(via SPORT1).

 

I setup and run DMA0 PPI:

*pDMA0_CONFIG = 0; // обнуляем настройки DMA0

*pDMA0_PERIPHERAL_MAP = 0x0000; // подключаем DMA0 для PPI
*pDMA0_NEXT_DESC_PTR = &LCD_descriptor_array[9];

*pDMA0_START_ADDR = &LCDActivePage[0];
*pDMA0_X_COUNT = LCD_descriptor_array[5];
*pDMA0_X_MODIFY = LCD_descriptor_array[6];
*pDMA0_Y_COUNT = LCD_descriptor_array[7];
*pDMA0_Y_MODIFY = LCD_descriptor_array[8];
*pDMA0_CONFIG = LCD_descriptor_array[4]; // DMA enable...

 

*pTIMER_DISABLE = 0xFF;
*pTIMER_STATUS = 0xFFFF;
*pTIMER0_CONFIG = 0x02B9;
*pTIMER1_CONFIG = 0x02B9;
*pTIMER0_WIDTH = 10;

*pTIMER0_PERIOD = 760;
*pTIMER1_WIDTH = 2*760;

*pTIMER1_PERIOD = 328*760;

*pTIMER5_CONFIG = 0x0219;
*pTIMER5_WIDTH = 4;
*pTIMER5_PERIOD = 8;

asm("ssync;");

*pPPI_STATUS = 0;
*pPPI_DELAY = 19;

*pPPI_COUNT = 759;
*pPPI_CONTROL = 0xC01F; // PPI enable...

*pTIMER_ENABLE = 0x3|(1<<5); // running...

 

LCDActivePage array is in SDRAM.

 

And I setup and run DMA5 SPORT1:

*pPORTF_FER |= (1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<13);
*pPORTF_MUX |= (1<<8)|(1<<6)|(1<<4)|(1<<2);
*pSPORT1_RFSDIV = 255; // 512 SCLK for one frame
*pSPORT1_TFSDIV = 255; // 512 SCLK for one frame...
*pSPORT1_MCMC1 = 0x0000; // 8 active channel...
*pSPORT1_MCMC2 = 0x0010; // DMA enable...
*pSPORT1_MRCS0 = 0x000F;

*pDMA5_CONFIG = 0;

*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_START_ADDR = &ADC_Buffer[0];
*pDMA5_X_COUNT = 256*8;
*pDMA5_X_MODIFY = 4;
*pDMA5_CONFIG = 0x108B;

*pSPORT1_TCR2 = 0x0017;
*pSPORT1_RCR2 = 0x0017; // 16-bit...

*pSIC_IAR2 = (*pSIC_IAR2&0x0FFFFFFF)|(2<<8); // DMA5 RX ISR - ivg9 (5)...
register_handler(ik_ivg9, ADC_ISR); // assign ISRs to interrupt vectors

*pSIC_IMASK0 |= (1<<18); // enable ADC ISR

 

*pSPORT1_RCR1 = 0x4205; // running...
*pSPORT1_TCR1 = 0x4001; // running...

 

ADC_Buffer - also is in SDRAM.

 

If I running only DMA0 PPI - all is ok. If I running only DMA5 SPORT1 - all is ok.

But when at first I running DMA0 PPI, after that I running DMA5 SPORT1, DMA0 stops and all DMA0 reg's - is zero.

 

What could be wrong?

 

Thanks.

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