I have an ATV motherboard (Rev B) with a ADV7842EBZ Rev C at the input and a ATV OPxZ Rev E at the output.
When I use high resolution like 1600x1200@60 or 1920x1080@60 Reduced Blanking I have timing problems between ADV7842 and Xilinx FPGA and/or timing problem with Xilinx FPGA and ADV7511.
Signal input is coming from HD15 and is output through HDMI to a screen. I use "5_5b_1600x1200_60_UXGA_RGB_in_444_24bit_H_V_DE_HDMI" script for 1600x1200@60 and "5_8b_1920x1080_60_with_reduced_blanking_RGB_in_444_24bit_H_V_DE_DVI" for 1920x1080@60RB.
I have DVP evaluation software version 1.5.
I have done the same operations on EVAL-ADV7842-7511 board and there is no problems (except the disturbances that I already spoken cf. "ADV7842 Analog inputs disturbances").