A processor with SPORT has to receive data from an ASIC at 16kbps. It should send data to the same ASIC at 4.8kbps. In ASIC, there are only clock and data lines available for transmission and reception. So I chose, SPORT interface.
For experiment, I am interfacing 2 same processors(that have 2 SPORT peripherals).
Being one as transmitter of data and another as receiver. The transmit clock is 16kHz. For transmit side,control register is programmed with:
M_SPCTL0 = 0x028355F9;
M_DIV0 = 0x00000AFB;
Each time 32 bits are transmitted. Frame sync is not connected.
For receive side, control register programmed with :
M_SPCTL1 = 0x008351F9;
In receiving processor, I am configuring SPORT interrupt with highest priority. As per my understanding, an interrupt is generated as soon as it receives 32 bits. Right now with only SPORT interrupt enabled, I am receiving data properly. During data reception, if transmitting processor is issued reset and started transmission through SPORT freshly, then the data received was not proper(looks like a junk data).
What could be the problem?
What happens if frame sync is not at all used?
If frame sync required bit is not set in SPCTL register, what should be the value of IFS, LFS, LAFS bits ?
Images of SPCTL register details are attached.
Let me know if any other details required.