Our setup has the ADF4355/ADF5355 in integer N mode with divided feedback to produce a freq at 1550MHz.
Ref = 25Mhz
R = 1 (reference doubler and div are disabled)
N = 62
D = 4
Frac1=Frac2 = 0
With the above setup we expect to see the output be phase locked to the reference. However we typically see the output at 2 difference phase location with respect to reference when we run the freq update routine. It seems to generally favor one over the other. We have this issues on the eval board as well as in our system.
-Running autocal will sometimes cause the output phase to jump between the 2 aforementioned outputs, however sometimes only running the freq update routine will cause a jump.
-Increasing CP current will decrease the distance that the phase jumps.
-Increasing timeout values reduces the occurrence of the phase jump.
-Some N values appear to not have this issue - or the occurrence is reduced.
-D value of 2 or 1 appear to not have this issue - or the occurrence is reduced.
-Sometime planning around with the ADC values (changing div, disbaling reenabling), and then returning the ADC values to their original value will cause this issue to go away as well. However we have not found a set of instructions that make this deterministic.
It appears that there may be an issue with some hidden subsystem. AFAIK integer N setups where R is 1 should have unconditional phase relationship with respect to the reference.
Is there anyway we can get unconditional phase relationship with the described setup?