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User guide for no-os fmcdaq2

Question asked by cswanson on Sep 12, 2017
Latest reply on Sep 14, 2017 by andrei_g

In order for me to understand the details motivation behind the code written for the hdl (hdl_2016_r2) and no-os (2016_R2) for the fmcdaq2 and kcu105, I added comments as the code is executing.  As you can see, there is a lot of code.  Is there any user guide and documentation as to why the registers were set this way?  The only alternative I see is for me to study the daq2 schematics, data sheets, and C code to decipher the algorithm.  I have attached a file with the exact output from running the golden code and then the same run with my comments added.

Thanks,

Craig

 

Here is the "golden version": 

adc_setup adc core initialized (1000 MHz).
dac_setup dac core initialized (1000 MHz).
ad9144_status : check-sum MISMATCH (0)!.
daq2: transmit data from memory
daq2: RX capture done.

 

Here is the same code where I added a bunch of ad_printf statements so I could somewhat understand what is going on:

Setup GPIOs
1: ad_gpio_set(GPIO_CLKD_SYNC, 0);
2: ad_gpio_set(GPIO_DAC_RESET, 0);
3: ad_gpio_set(GPIO_DAC_TXEN, 0);
4: ad_gpio_set(GPIO_ADC_PD, 1);
5: mdelay(5);
6: ad_gpio_set(GPIO_CLKD_SYNC, 1);
7: ad_gpio_set(GPIO_DAC_RESET, 1);
8: ad_gpio_set(GPIO_DAC_TXEN, 1);
9: ad_gpio_set(GPIO_ADC_PD, 0);
B: setup clocks by calling ad9523_setup
1: Beginning ad9523_setup
2: ad9523_spi_write A BUNCH OF STUFF I DON'T UNDERSTAND
3: mdelay(1);
4: ad9523_spi_write(dev, AD9523_READBACK_CTRL,
5: ad9523_io_update(dev);
6: ad9523_spi_read(dev, AD9523_EEPROM_CUSTOMER_VERSION_ID, &version_i
7: ad9523_spi_write(dev, AD9523_EEPROM_CUSTOMER_VERSION_ID, 0xAD95);
8: ad9523_spi_read(dev, AD9523_EEPROM_CUSTOMER_VERSION_ID, &reg_data)
9: AD9523: SPI write-verify failed
10: ad9523_spi_write(dev, AD9523_EEPROM_CUSTOMER_VERSION_ID, version_
11a: PLL1 Setup
11b: ad9523_spi_write(dev, AD9523_PLL1_REF_A_DIVIDER,
12: ad9523_spi_write(dev, AD9523_PLL1_REF_B_DIVIDER,
13: ad9523_spi_write(dev, AD9523_PLL1_FEEDBACK_DIVIDER,
14: ad9523_spi_write(dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
15: ad9523_spi_write(dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
16: ad9523_spi_write(dev, AD9523_PLL1_REF_CTRL,
17: ad9523_spi_write(dev, AD9523_PLL1_MISC_CTRL,
18: ad9523_spi_write(dev, AD9523_PLL1_LOOP_FILTER_CTRL,
19a: PLL2 Setup
19b: ad9523_spi_write(dev, AD9523_PLL2_CHARGE_PUMP,
20: ad9523_spi_write(dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
21: ad9523_spi_write(dev, AD9523_PLL2_CTRL,
22: ad9523_spi_write(dev, AD9523_PLL2_VCO_CTRL,
23: ad9523_spi_write(dev, AD9523_PLL2_VCO_DIVIDER,
24: ad9523_spi_write(dev, AD9523_PLL2_R2_DIVIDER,
25: ad9523_spi_write(dev, AD9523_PLL2_LOOP_FILTER_CTRL,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
26: ad9523_spi_write(dev,
27: ad9523_vco_out_map(dev, chan->channel_num,
28: ad9523_spi_write(dev,
28: ad9523_spi_write(dev,
28: ad9523_spi_write(dev,
28: ad9523_spi_write(dev,
28: ad9523_spi_write(dev,
28: ad9523_spi_write(dev,
29: ad9523_spi_write(dev, AD9523_POWER_DOWN_CTRL, 0);
30: ad9523_spi_write(dev, AD9523_STATUS_SIGNALS,
31: ad9523_io_update(dev);
32: ad9523_sync(dev);
33: ad9523_spi_write(dev, AD9523_READBACK_CTRL, 0x0);
34: ad9523_io_update(dev);
35: ad9523_calibrate(dev);
36: ad9523_sync(dev);
37: Finished with ad9523_setup;
C: setup the devices by calling ad9680_setup
1: Beginning ad9680_setup
2: ad9680_spi_read(dev, AD9680_REG_CHIP_ID_LOW, &chip_id);
3: ad9680_spi_write(dev, AD9680_REG_INTERFACE_CONF_A, 0x81);
4: ad9680_spi_write(dev, AD9680_REG_LINK_CONTROL, 0x15);
5: ad9680_spi_write(dev, AD9680_REG_JESD204B_CSN_CONFIG, 0x2d);
6: ad9680_spi_write(dev, AD9680_REG_JESD204B_CSN_CONFIG, 0x2d);
7: ad9680_spi_write(dev, AD9680_REG_JESD204B_SUBCLASS_CONFIG, 0x2f);
8: ad9680_spi_write(dev, AD9680_REG_JESD204B_QUICK_CONFIG, 0x88);
10: ad9680_spi_write(dev, AD9680_REG_JESD204B_LANE_RATE_CTRL, 0x00)
11: ad9680_spi_write(dev, AD9680_REG_LINK_CONTROL, 0x14);
12: mdelay(250);
13: ad9680_spi_read(dev, AD9680_REG_JESD204B_PLL_LOCK_STATUS, &pll_st
14: Finishing ad9680_setup
D: setup the devices by calling ad9144_setup
1: Entering ad9144_setup
1b: ad9144_spi_read(dev, REG_SPI_PRODIDL, &chip_id);
2: ad9144_spi_write(dev, REG_SPI_SCRATCHPAD, 0xAD);
3: ad9144_spi_read(dev, REG_SPI_SCRATCHPAD, &scratchpad);
4: ad9144_spi_write(dev, REG_SPI_INTFCONFA, SOFTRESET_M | SOFTRESET);
5: ad9144_spi_write(dev, REG_SPI_INTFCONFA, 0x00);
6: mdelay(1);
7: ad9144_spi_write(dev, REG_PWRCNTRL0, 0x00);
8: ad9144_spi_write(dev, REG_CLKCFG0, 0x00);
9: ad9144_spi_write(dev, REG_SYSREF_ACTRL0, 0x00);
10: ad9144_spi_write(dev, REG_DATA_PATH_FLUSH_COUNT0, 0x8b);
11: ad9144_spi_write(dev, REG_BLSM_CTRL, 0x01);
12: ad9144_spi_write(dev, REG_DEV_CONFIG_8, 0xff);
13: ad9144_spi_write(dev, REG_DACPLLT17, 0x73);
14: ad9144_spi_write(dev, REG_SERDES_PLL_CTRL, 0x49);
15: ad9144_spi_write(dev, REG_SERDES_PLL_CP3, 0x24);
16: ad9144_spi_write(dev, REG_SERDES_PLL_VAR3, 0x73);
17: ad9144_spi_write(dev, REG_CONFIG_REG3, 0xff);
18: ad9144_spi_write(dev, REG_DEVICE_CONFIG_REG_13, 0x01);
19: ad9144_spi_write(dev, REG_INTERP_MODE, 0x00);
20: ad9144_spi_write(dev, REG_DATA_FORMAT, 0x00);
21: ad9144_spi_write(dev, REG_MASTER_PD, 0x00);
22: ad9144_spi_write(dev, REG_PHY_PD, 0x00);
23: ad9144_spi_write(dev, REG_GENERAL_JRX_CTRL_0, 0x01);
24: ad9144_spi_write(dev, REG_ILS_DID, 0x00);
25: ad9144_spi_write(dev, REG_ILS_BID, 0x00);
26: ad9144_spi_write(dev, REG_ILS_LID0, 0x04);
27: ad9144_spi_write(dev, REG_ILS_SCR_L, 0x83);
28: ad9144_spi_write(dev, REG_ILS_F, 0x00);
29: ad9144_spi_write(dev, REG_ILS_K, 0x1f);
30: ad9144_spi_write(dev, REG_ILS_M, 0x01);
31: ad9144_spi_write(dev, REG_ILS_CS_N, 0x0f);
32: ad9144_spi_write(dev, REG_ILS_NP, 0x2f);
33: ad9144_spi_write(dev, REG_ILS_S, 0x20);
34: ad9144_spi_write(dev, REG_ILS_HD_CF, 0x80);
35: ad9144_spi_write(dev, REG_ILS_CHECKSUM, 0x49);
36: ad9144_spi_write(dev, REG_LANEDESKEW, 0x0f);
37: ad9144_spi_write(dev, REG_CTRLREG1, 0x01);
38: ad9144_spi_write(dev, REG_LANEENABLE, 0x0f);
39: ad9144_spi_write(dev, REG_DEV_CONFIG_9, 0xb7);
40: ad9144_spi_write(dev, REG_DEV_CONFIG_10, 0x87);
41: ad9144_spi_write(dev, REG_DEV_CONFIG_11, 0xb7);
42: ad9144_spi_write(dev, REG_DEV_CONFIG_12, 0x87);
43: ad9144_spi_write(dev, REG_TERM_BLK1_CTRLREG0, 0x01);
44: ad9144_spi_write(dev, REG_TERM_BLK2_CTRLREG0, 0x01);
45: ad9144_spi_write(dev, REG_SERDES_SPI_REG, 0x01);
45b: ad9144_spi_write(dev, REG_CDR_OPERATING_MODE_REG_0, 0x28);
46: ad9144_spi_write(dev, REG_CDR_RESET, 0x00);
47a: ad9144_spi_write(dev, REG_CDR_RESET, 0x01);
47c: ad9144_spi_write(dev, REG_REF_CLK_DIVIDER_LDO, 0x04);
48: ad9144_spi_write(dev, REG_SYNTH_ENABLE_CNTRL, 0x01);
49: ad9144_spi_write(dev, REG_SYNTH_ENABLE_CNTRL, 0x05);
50: mdelay(20);
51: ad9144_spi_write(dev, REG_EQ_BIAS_REG, 0x62);
52: ad9144_spi_write(dev, REG_GENERAL_JRX_CTRL_1, 0x01);
53: ad9144_spi_write(dev, REG_LMFC_DELAY_0, 0x00);
54: ad9144_spi_write(dev, REG_LMFC_DELAY_1, 0x00);
55: ad9144_spi_write(dev, REG_LMFC_VAR_0, 0x0a);
56: ad9144_spi_write(dev, REG_LMFC_VAR_1, 0x0a);
57: ad9144_spi_write(dev, REG_SYNC_CTRL, 0x01);
58: ad9144_spi_write(dev, REG_SYNC_CTRL, 0x81);
59: ad9144_spi_write(dev, REG_SYNC_CTRL, 0xc1);
60: ad9144_spi_write(dev, REG_GENERAL_JRX_CTRL_0, 0x01);
61: ad9144_spi_write(dev, REG_CAL_CLKDIV, 0x38);
62: ad9144_spi_write(dev, REG_CAL_INIT, 0xa6);
63: ad9144_spi_write(dev, REG_CAL_INDX, 0x03);
64: ad9144_spi_write(dev, REG_CAL_CTRL, 0x01);
65: ad9144_spi_write(dev, REG_CAL_CTRL, 0x03);
66: mdelay(10);
67: ad9144_spi_write(dev, REG_CAL_INDX, 0x01);
68: ad9144_spi_check_status(dev, REG_CAL_CTRL, 0xc0, 0x80);
69: ad9144_spi_write(dev, REG_CAL_INDX, 0x02);
70: ad9144_spi_check_status(dev, REG_CAL_CTRL, 0xc0, 0x80);
71: ad9144_spi_write(dev, REG_CAL_CLKDIV, 0x30);
72: Finishing ad9144_setup
E: set up the JESD core for ad9680
1: Entering jesd_setup(jesd_core core)
2: jesd_write(core, JESD204_REG_TRX_RESET, JESD204_TRX_GT_WDT_DIS
3: jesd_write(core, JESD204_REG_TRX_ILA_SUPPORT, JESD204_TRX_ILA_EN
4: jesd_write(core, JESD204_REG_TRX_SCRAMBLING, core.scramble_enable)
5: jesd_write(core, JESD204_REG_TRX_SYSREF_HANDLING, JESD204_TRX_SYSR
6: jesd_write(core, JESD204_REG_TRX_OCTETS_PER_FRAME,JESD204_TRX_OCTE
7: jesd_write(core, JESD204_REG_TRX_FRAMES_PER_MULTIFRAME,
8: jesd_write(core, JESD204_REG_TRX_SUBCLASS_MODE,
9: Finishing jesd_setup(jesd_core core)
F: set up the JESD core for ad9144
1: Entering jesd_setup(jesd_core core)
2: jesd_write(core, JESD204_REG_TRX_RESET, JESD204_TRX_GT_WDT_DIS
3: jesd_write(core, JESD204_REG_TRX_ILA_SUPPORT, JESD204_TRX_ILA_EN
4: jesd_write(core, JESD204_REG_TRX_SCRAMBLING, core.scramble_enable)
5: jesd_write(core, JESD204_REG_TRX_SYSREF_HANDLING, JESD204_TRX_SYSR
6: jesd_write(core, JESD204_REG_TRX_OCTETS_PER_FRAME,JESD204_TRX_OCTE
7: jesd_write(core, JESD204_REG_TRX_FRAMES_PER_MULTIFRAME,
8: jesd_write(core, JESD204_REG_TRX_SUBCLASS_MODE,
9: Finishing jesd_setup(jesd_core core)
G: set up the XCVRs
G1: DAC_XCVR controls the QPLL reset. First calling ad9144
1: Entering xcvr_setup in xcvr_core.c
3: xcvr_write(core, XCVR_REG_RESETN, XCVR_RESETN);
4: xcvr_read(core, XCVR_REG_STATUS, &status);
1: Finishing xcvr_setup in xcvr_core.c
1: Entering xcvr_setup in xcvr_core.c
3: xcvr_write(core, XCVR_REG_RESETN, XCVR_RESETN);
4: xcvr_read(core, XCVR_REG_STATUS, &status);
1: Finishing xcvr_setup in xcvr_core.c
H: Check jesd status of ad9144
1: Entering jesd_status(jesd_core core)
2: jesd_read(core, JESD204_REG_TRX_RESET, &status);
4: jesd_read(core, JESD204_REG_TRX_SYNC_STATUS, &status);
6: jesd_read(core, JESD204_REG_TRX_SYNC_STATUS, &status);
I: Check jesd status of ad9680
1: Entering jesd_status(jesd_core core)
2: jesd_read(core, JESD204_REG_TRX_RESET, &status);
4: jesd_read(core, JESD204_REG_TRX_SYNC_STATUS, &status);
6: jesd_read(core, JESD204_REG_TRX_SYNC_STATUS, &status);
8: jesd_read(core, JESD204_REG_RX_LINK_ERROR_STATUS, &status);
1: Finishing jesd_status(jesd_core core)
J: interface core setup for ad9680
1: Entering adc_setup
2: adc_read(core, ADC_REG_ID, &reg_data);
3: adc_write(core, ADC_REG_RSTN, 0);
4: adc_write(core, ADC_REG_RSTN, ADC_MMCM_RSTN | ADC_RSTN);
5: adc_write(core, ADC_REG_CHAN_CNTRL(index), PLUS EXTRA STUFF
5: adc_write(core, ADC_REG_CHAN_CNTRL(index), PLUS EXTRA STUFF
6: mdelay(100);
7a: adc_read(core, ADC_REG_STATUS, &reg_data);
8: adc_read(core, ADC_REG_CLK_FREQ, &adc_clock);
9: adc_read(core, ADC_REG_CLK_RATIO, &reg_data);
10: adc_setup adc core initialized (1000 MHz).
11: Finishing ADC setup
J: interface core setup for ad9144
1: Entering dac_setup
2: dac_write(core, DAC_REG_RSTN, 0x00);
3: dac_write(core, DAC_REG_RSTN, 0x03);
4: mdelay(100);
5: dac_read(core, DAC_REG_STATUS, &reg_data);
6: dac_read(core, DAC_REG_CLK_FREQ, &dac_clock);
7: dac_read(core, DAC_REG_CLK_RATIO, &reg_data);
8: dac_setup dac core initialized (1000 MHz).
9: Calling dac_data_setup(core)
1: Entering dac_data_setup
2: dds_set_frequency(core, ((i*2)+0), chan->dds_frequency_0);
3: dds_set_phase(core, ((i*2)+0), chan->dds_phase_0);
4: dds_set_scale(core, ((i*2)+0), chan->dds_scale_0);
5: dds_set_frequency(core, ((i*2)+0), chan->dds_frequency_0);
6: dds_set_phase(core, ((i*2)+0), chan->dds_phase_0);
7: dds_set_scale(core, ((i*2)+0), chan->dds_scale_0);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
2: dds_set_frequency(core, ((i*2)+0), chan->dds_frequency_0);
3: dds_set_phase(core, ((i*2)+0), chan->dds_phase_0);
4: dds_set_scale(core, ((i*2)+0), chan->dds_scale_0);
5: dds_set_frequency(core, ((i*2)+0), chan->dds_frequency_0);
6: dds_set_phase(core, ((i*2)+0), chan->dds_phase_0);
7: dds_set_scale(core, ((i*2)+0), chan->dds_scale_0);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
13: Finishing dac_data_setup
10: Finishing dac_setup
K: check status of ad9144
1: Entering ad9144_status: check for jesd status on all lanes
2: ad9144_spi_read(dev, REG_CODEGRPSYNCFLG, &status);
4: ad9144_spi_read(dev, REG_CODEGRPSYNCFLG, &status);
6: ad9144_spi_read(dev, REG_CODEGRPSYNCFLG, &status);
8: ad9144_spi_read(dev, REG_CODEGRPSYNCFLG, &status);
10: Finishing ad9144_status
L: Entering transport path testing
M: transport path testing
1: Entering dac_data_setup
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
13: Finishing dac_data_setup
N: dac_data_setup(&ad9144_core);
1: Entering ad9144_short_pattern_test
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
2: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
3: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_2, (init_param.stpl_sampl
4: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_1, (init_param.stpl_sampl
5: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
6: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
7: ad9144_spi_write(dev, REG_SHORT_TPL_TEST_0, ((sample << 4) | (dac
9: Leaving ad9144_short_pattern_test
O: Beginning PN7 data path test
P1: dac_data_setup(&ad9144_core);
1: Entering dac_data_setup
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
13: Finishing dac_data_setup
P2: ad9144_datapath_prbs_test(&ad9144_spi_device, ad9144_param);
1: Entering ad9144_datapath_prbs_test
2: ad9144_spi_write(dev, REG_PRBS, ((init_param.prbs_type << 2) | 0x0
3: ad9144_spi_write(dev, REG_PRBS, ((init_param.prbs_type << 2) | 0x0
4: mdelay(500);
5: ad9144_spi_write(dev, REG_SPI_PAGEINDX, 0x01);
6: ad9144_spi_read(dev, REG_PRBS, &status);
8a: ad9144_spi_read(dev, REG_PRBS_ERROR_I, &status);
9a: ad9144_spi_read(dev, REG_PRBS_ERROR_Q, &status);
10: Finishing ad9144_datapath_prbs_test
Q1: Beginning PN15 data path test
Q2: dac_data_setup(&ad9144_core);
1: Entering dac_data_setup
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
13: Finishing dac_data_setup
Q3: ad9144_datapath_prbs_test(&ad9144_spi_device, ad9144_param);
1: Entering ad9144_datapath_prbs_test
2: ad9144_spi_write(dev, REG_PRBS, ((init_param.prbs_type << 2) | 0x0
3: ad9144_spi_write(dev, REG_PRBS, ((init_param.prbs_type << 2) | 0x0
4: mdelay(500);
5: ad9144_spi_write(dev, REG_SPI_PAGEINDX, 0x01);
6: ad9144_spi_read(dev, REG_PRBS, &status);
8a: ad9144_spi_read(dev, REG_PRBS_ERROR_I, &status);
9a: ad9144_spi_read(dev, REG_PRBS_ERROR_Q, &status);
10: Finishing ad9144_datapath_prbs_test
R: Beginning receive path testing
S1: ad9680_test(&ad9680_spi_device, AD9680_TEST_PN9);
1: Entering ad9680_test
2: ad9680_spi_write(dev, AD9680_REG_ADC_TEST_MODE, test_mode);
4: ad9680_spi_write(dev, AD9680_REG_OUTPUT_MODE, AD9680_FORMAT_OFFSET
5: Finishing ad9680_test
T1: ad9680_test(&ad9680_spi_device, AD9680_TEST_PN23);
1: Entering ad9680_test
2: ad9680_spi_write(dev, AD9680_REG_ADC_TEST_MODE, test_mode);
4: ad9680_spi_write(dev, AD9680_REG_OUTPUT_MODE, AD9680_FORMAT_OFFSET
5: Finishing ad9680_test
U1: Beginning default data;
U2: dac_data_setup(&ad9144_core);
1: Entering dac_data_setup
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
11: dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data);
12: dac_data_src_sel(core, i, chan->sel);
13: Finishing dac_data_setup
U3: daq2: transmit data from memory
Y: external loopback - capture data with DMA
Z: ad9680_test(&ad9680_spi_device, AD9680_TEST_OFF);
1: Entering ad9680_test
2: ad9680_spi_write(dev, AD9680_REG_ADC_TEST_MODE, test_mode);
3: ad9680_spi_write(dev, AD9680_REG_OUTPUT_MODE, AD9680_FORMAT_2S_COM
5: Finishing ad9680_test
AA: daq2: RX capture done.
Finished with overall system test

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